Date: Fri, 12 Feb 2021 10:27:09 -0600
Regarding use of volatile and compound assignments, I can provide a few
comments.
A project I worked on previously involved communicating between a GPP and
FPGA (a system-on-chip). We communicated with the FPGA via memory mapping
of the FPGA "registers" to RAM (note, I will use the term "register" for
the memory-mapped locations in the FPGA after this point). As such, any
accesses to those FPGA registers were volatile. I thought for sure we did
compound assignments all the time. However, I took a look today and
compound assignment is less frequent than I thought.
The main reason we don't *always* use compound assignment for bit twiddling
is what I will call "coherence" of the operations. If for any reason the
operation might result in multiple writes to the register, we would do
those on a temporary and then write. In some cases, registers were backed
by FIFO queues. We could not allow writing of partial results of a word
into that register. We also would use a temporary to perform complex bit
masking needed to be done. I should also note that we had locking at a
higher level, so there was no threading concern for these operations. Our
primary issue was ensuring that the writes to the FPGA were coherent.
Daniel
comments.
A project I worked on previously involved communicating between a GPP and
FPGA (a system-on-chip). We communicated with the FPGA via memory mapping
of the FPGA "registers" to RAM (note, I will use the term "register" for
the memory-mapped locations in the FPGA after this point). As such, any
accesses to those FPGA registers were volatile. I thought for sure we did
compound assignments all the time. However, I took a look today and
compound assignment is less frequent than I thought.
The main reason we don't *always* use compound assignment for bit twiddling
is what I will call "coherence" of the operations. If for any reason the
operation might result in multiple writes to the register, we would do
those on a temporary and then write. In some cases, registers were backed
by FIFO queues. We could not allow writing of partial results of a word
into that register. We also would use a temporary to perform complex bit
masking needed to be done. I should also note that we had locking at a
higher level, so there was no threading concern for these operations. Our
primary issue was ensuring that the writes to the FPGA were coherent.
Daniel
Received on 2021-02-12 10:27:22