> Indeed. Do note that a lockfree CAS isn't enough: there needs to be an
atomic
way of loading and storing 128 bits, which is lacking a dedicated
instruction
on x86-64. Without that, one must lock and unlock to perform loads and
stores.

I'd note that this is not quite true - you can implement load/store using
CAS (as long as you aren't doing a load on read-only memory). Store is just
`T control = 0; while(this->compare_exchange_weak(control, val,
memory_order::relaxed, order);`. Load is even simpler and is just
```
T val = 0;
this->compare_exchange_weak(val, 0, order, order);
return val;
```

LLVM at least does this codegen for 8-byte atomics on 32-bit x86 without
either mmx or x87 (but with cx8).

On Thu, 1 Jan 2026 at 12:24, Thiago Macieira via Std-Proposals <
std-proposals_at_[hidden]> wrote:

> On Thursday, 1 January 2026 13:09:55 Brasilia Standard Time Jonathan
> Wakely
> via Std-Proposals wrote:
> > >> Intel: All Intel x86_64 CPUs include CMPXCHG16B
> > >
> > > Nocona doesn't, as far as I know
> >
> > Nor some low-power processors like early Atom models, and apparently
> modern
> > ones including Novalake which is due to launch later in 2026.
>
> Early Atoms and Core, maybe. But the earliest available in the SDE tool
> (Saltwell) already does:
>
> $ /opt/intel/sde-external-9.44.0-2024-08-22-lin/sde64 -slt -- cpuid -1l1
> |
> grep CMPXCHG
> CMPXCHG8B inst. = true
> CMPXCHG16B instruction = true
>
> And while I have not got my hands on a NVL, I know it will have CX16.
>
> Frederick may have a point if OSes no longer support booting without CX16
> (apparently, Windows doesn't). But he's still forgetting the AVX bit for
> atomic 128-bit loads.
>
> --
> Thiago Macieira - thiago (AT) macieira.info - thiago (AT) kde.org
> Principal Engineer - Intel Data Center - Platform & Sys. Eng.
> --
> Std-Proposals mailing list
> Std-Proposals_at_[hidden]
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>