> There is hardware support for 64/128-bit mixed operations.
>std::float128_t can also be used to implement any integer operation up to 113 bits. RISC-V has a RV128I variant.

113bits is 15bits short of 128, and "64/128-bit mixed operations " isn't the same thing as "128-bit operations".

> I'm not sure what you think qualifies for "native support". There is more than enough native support. While it is not typical to choose a 128-bit general purpose register size (and likely won't be common in the foreseeable future), some degree of 128-bit arithmetic support is already common.

Having a "128-bit general purpose register" would be my definition of "native support".


> I know all of that. The proposal explains that there is hardware support for these widening operations, and that this extends further to multi-precision arithmetic.

Again, it’s X Y problem. You want 128bit because some crypto libraries use it for multi-word arithmetic, not because 128bit is useful.


> Just because you need more than 128 bits...

It means that having 128bits won't fix your problem. Your problem is something else. I.e. why I'm pointing out that this is the X Y issue. What you want is to be able to write algorithms for arbitrary width integers, but what you are asking is 128bits to implement multi-precision arithmetic.
 
I'm going to skip NVIDIA CUDA support, as those run on your GPU not CPU.


My suggestion would be to remove the stuff related to multi-precision arithmetic from the motivation first and see what's left. I think you will find that it is not allot.