Hello all,

My name is Kamalesh Lakkampally, founder of an EDA startup,  I am submitting the attached draft proposal (PnnnnR0) for consideration by the Evolution Working Group (EWG).
This proposal introduces a provisional core-language extension enabling fetch-only instructions—instructions that operate entirely in the processor’s fetch stage and use a dedicated path outside the normal execution pipeline.

The goal is to support workloads where the execution order of micro-tasks changes dynamically and unpredictably every cycle, such as event-driven HDL/SystemVerilog simulation.
In such environments, conventional C++ mechanisms (threads, coroutines, futures, indirect calls, executors) incur significant pipeline redirection penalties. Fetch-only instructions aim to address this problem in a structured, language-visible way.

I would greatly appreciate feedback, criticism, and suggestions from the community.
I am also open to collaboration.

This is an early-stage concept, and I welcome any guidance on improving the design, refining the semantics, or adapting the idea to better align with the C++ abstract machine and WG21 process.

Thank you for your time, and I look forward to your comments.