The implementation can advantageously use special registers on FPGAs or specialized computation units/accelerators, it can be used on modern PCs with less than 64 bytes alignment, independent of the cache architecture. Perhaps some alignment can help with performance, but to have a large alignment (normally) is not necessary.
The horse is alive and kicking (even a capriole).
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Von: Tiago Freire <tmiguelf@hotmail.com>
Gesendet: Fr 05.09.2025 15:22
Betreff: Re: [std-proposals] D3666R0 Bit-precise integers
An: std-proposals@lists.isocpp.org;
CC: Sebastian Wittmeier <wittmeier@projectalpha.org>;
The argument was that it could be used to represent specialized registers, it can't. Why are we still beating this dead horse?
From: Std-Proposals <std-proposals-bounces@lists.isocpp.org> on behalf of Sebastian Wittmeier via Std-Proposals <std-proposals@lists.isocpp.org>
Sent: Friday, September 5, 2025 1:05:01 PM
To: std-proposals@lists.isocpp.org <std-proposals@lists.isocpp.org>
Cc: Sebastian Wittmeier <wittmeier@projectalpha.org>
Subject: Re: [std-proposals] D3666R0 Bit-precise integersNobody (?) said it has to be done with a single store/load.
384 bits are 3x16 bytes.
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Von: Tiago Freire via Std-Proposals <std-proposals@lists.isocpp.org>
Gesendet: Fr 05.09.2025 11:34
Betreff: Re: [std-proposals] D3666R0 Bit-precise integers
An: David Brown <david.brown@hesbynett.no>; std-proposals@lists.isocpp.org;
CC: Tiago Freire <tmiguelf@hotmail.com>;
And yet you don't understand that in some CPUs store/loads cannot strut across cache lines.This is something that a CPU may not have the circuitry to physically do.-- Std-Proposals mailing list Std-Proposals@lists.isocpp.org https://lists.isocpp.org/mailman/listinfo.cgi/std-proposals