I propose to restrict possible values of CHAR_BIT to be 8 * (2 ^ n)
where n is a non-negative integer.

This gives values of 8, 16, 32, 64, 128 and so on.

I have surveyed the most likely hardware architectures that would not
fit with this restriction - computers with 24 bit bytes i.e. where
CHAR_BIT == 24.

The most extensive information I could find is on Wikipedia:

https://en.wikipedia.org/wiki/24-bit
https://en.wikipedia.org/wiki/Category:24-bit_computers

It seems like the only candidate that is still relevant is Motorola
56000 series:

https://en.wikipedia.org/wiki/Motorola_56000

However, the specification says that it uses 8 bit bytes:

http://cache.freescale.com/files/dsp/doc/inactive/DSP56000UM.pdf

Therefore, I couldn't find implementations where CHAR_BIT == 24 which
means other more exotic cases probably never existed.