Date: Fri, 5 Sep 2025 21:18:52 +0000
> alignof(__m512i) = 64bytes
Interesting. That seems to be for performance reasons, since it's not required by hardware.
Note that the alignment of this type is 16 using GCC.
See: https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_load*si512&ig_expand=5883,223,4019,4019,4103&avx512techs=AVX512F&cats=Load
Note that both assembly instructions, movaps and movups, have the same latency on the listed hardware (when the address is 64B-aligned).
That's not necessarily true on older hardware (e.g., sandybridge), which one might guess explains why there are two instructions.
Received on 2025-09-05 21:18:54