On 7/19/22 11:52, Andy Wang via Std-Discussion wrote:
>> if the wait is woken by the notify there is no way it doesn't
>> observe the store.
>
> Suppose you have
> ```
> X=0, Y=0
>
> T1:
> X.store(1, relaxed);
> Y.store(1, relaxed);
>
> T2:
> while Y.load(relaxed) != 1 {}
> r = X.load(relaxed);
> ```
>
> T1's Y.store is coherence ordered before the last Y.load in T2's loop.
> This does not mean r==1. If you run this on a real ARM CPU you can
> absolutely observe r==0.

Your example uses two atomic objects, each of them using its own
modification order. Without seq_cst memory order, their modification
orders are unordered between each other.

The original example uses a single atomic with its own single
modification order.