[ Adding SG5 ]
I do not know about Intel's plans. But the last couple of paragraphs of
https://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions are
not entirely consistent with the message about Intel's support that started
this thread. (AFAIK, HLE is not actually the most popular mechanism to
implement lock elision? The fact that it seems to have been dropped is less
interesting.)

If anyone has more details that they can repeat publicly, I would be
interested.

But I expect this is one of those areas in which we have a bit of a
catch-22 problem: It's hard to justify the hardware unless there are
applications. And the applications won't materialize unless TM is well
supported by programming languages, which we tend not to do until there is
hardware to make it efficient. IMO, it's worth another TS to see if we can
get ourselves out of this.

Hans

[ Please see the SG1 or EWG list for earlier parts of this thread. I
believe the SG5 archive is public, but the others are not? Hence I did not
include the earlier exchange here. Please include SG5 in your reply only if
this is OK with you. ]