On 4/25/24 21:49, David Goldblatt via Parallel wrote:
> Since some on this list don't follow the WG14 process, I thought I'd
> highlight this paper:
> https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3246.htm
>
> Since it's unlikely that such super-low-end processors will ever get a
> conforming C++ implementation, maybe it's not worth worrying too much about.

Well, I don't think they're much lower than 8-bit AVR, for which
there are at least two attempts to provide a fully conformant
implementation (maybe except exceptions...).

However, when this was originally discussed back for C++0x,
I've always claimed using disable interrupts is lockfree and
conforming and works well for single core.

My personal working definition for lockfree is:
"It can safely be used inside an interrupt service routine (ISR)."

For multi core I assume that any hardware will provide something
for synchronization that can be used inside ISRs.
I personally only know the hardware spinlocks on RP2040.

If one of them can be reserved for using by the implementation
exclusivly, then all should be fine as well.
There's only a problem of only a single such synchronization
hardware exists and it's undesirable to reserve its use for
the implementation.
I don't know if any of the hardware mentioned in N3246 has such
a problem.

   Detlef